The present invention relates to a semiconductor dynamic random access memory device having an internal refresh circuit, and more particularly to a test circuit for testing the operation of the internal refresh circuit.
The dynamic memory devices most widely used at present employ a large array of so-called "one-transistor dynamic memory cells" consisting of one IGFET (insulated gate field effect transistor) such as a MOS (metal oxide semiconductor) transistor, and one storage capacitor. Since the one-transistor memory cell is very small, a large-capacity memory device can be manufactured cheaply. However, the storage capacitors leak stored voltage. For this reason, each row line of the memory cell array should be accessed periodically to restore data in the memory cells. That is, the stored data should be refreshed.
From this purpose, the row address supplied to the memory device is changed by an externally provided address counter in synchronism with a row address strobe signal RAS, by which each row line of the memory cell array is accessed. This refresh mode is called RAS-refresh.
There is also a refresh mode called "internal refresh", in which an internal refresh circuit is provided in the memory device to produce a row address, and the memory cells connected to each row line are refreshed. This internal refresh circuit, which is widely used in memory devices, comprises a refresh timing circuit, an internal address counter and a timer circuit. The refresh timing circuit is controlled by the logic level at a refresh terminal which is provided for enabling the internal refresh mode. When the refresh terminal receives an enabling signal, the refresh timing circuit supplies the content of the internal address counter to a row address decoder as a row address, and thereby one row line of the memory cell array is accessed. The data stored in the memory cells connected to the accessed row line are read out and are then amplified by sense amplifiers, so that data identical to the read-out data are restored. When the data are restored, i.e., when the refresh operation is completed, the content of the internal address counter is increased or decreased by one, and the memory device stands by for a subsequent refresh operation. When the enabling level at the refresh terminal is inverted to be disabling, the internal refresh circuit is deactivated. Accordingly, memory operations, i.e., data read-out or data writing, are possible. When the refresh terminal receives an enabling signal again, the above-mentioned internal refresh operation is again carried out. Thus, the internal refresh operation is performed every time the refresh terminal receives an enabling signal, and therefore such a refresh mode is called "pulse-refresh operation". On the other hand, when the refresh terminal continuously receives an enabling signal, the timer circuit is activated to produce a refresh-request signal in a predetermined cycle. In response to this refresh-request signal, the refresh timing circuit supplies the increased or decreased content of the internal address counter to the row address decoder. As a result, the above-mentioned refresh operation is carried out, and the content of the internal address counter is further increased or decreased by one. As long as the refresh terminal receives an enabling signal, the timer circuit produces the refresh-request signal. Such a refresh mode is called a "self-refresh operation" in contrast to the pulse-refresh operation.
As described above, in memory devices having the internal refresh circuit, the content of the internal address counter is supplied to the row address decoder as a row address by sending an enabling signal to the refresh terminal, and the memory cells connected to the selected row line are refreshed. Accordingly. it is important for such a memory device that the internal refresh circuit operates accurately. Otherwise, the data stored in the memory cell may be destroyed and different data may replace it.
To test the operation of the internal refresh circuit, the prior art has utilized a decrease in the voltage stored in the storage capacitor of the memory cell due to the leak. The voltage stored in the storage capacitor is decreased, as a function of time, until it cannot be recognized whether the stored data is "1" or "0". The length of time necessary for the voltage to be lowered to such a level is called the "data-hold time". Even if the data-hold time is exceeded, the data stored in the memory cell is held by refreshing the memory cell periodically. Therefore, in the prior art, a "1" is written in all of the memory cells, and then the memory device is brought into the internal refresh mode to carry out the pulse-refresh operation or the self-refresh operation for a time exceeding the data-hold time. For the duration of the internal refresh mode, the row line selected by the internal address counter is changed in order each time the refresh terminal receives an enabling signal in the pulse-refresh operation, and also each time the timer circuit produces the refresh-request signal in the self-refresh operation, so that the memory cells connected to each row line are refreshed. When the internal refresh mode is completed, the data stored in all of the memory cells are read out. If " 0" is read out, the internal refresh circuit is judged to be inaccurate. Next, the data "0" is written into all of the memory cells, and the data is then read out of the respective memory cells after the internal refresh operation is completed. If the data "1" is read out, the internal refresh circuit is judged to be inaccurate.
The aforementioned prior art takes a relatively long time to test the internal refresh circuit. Specifically, the data-hold time of the memory cell is twenty to thirty seconds at room temperature. Accordingly, the internal refresh operation should be maintained for more than thirty seconds, so that the test time required for one memory device is more than one minute. The data-hold time is shortened in accordance with the increase in the ambient temperature. Accordingly, the test will end in several seconds if the test in operation of the internal refresh circuit is carried out at high temperature. However, special equipment for testing at high temperature is necessary. In addition, device characteristics caused by high temperatures influence the test.
In other words, prior art memory devices have not been equipped with circuits for testing the operation of the internal refresh circuits, necessitating the aforementioned relatively long test.